Modem computer systems are capable of executing various applications in parallel and require the ability to perform a context switch to allow for handling of an interrupt, task, or process switching. However, a significant bottleneck between processors and system memory exists. As a result, a substantial amount of latency is incurred for completion of the context switch for handling of an interrupt, task, or process switching
For example, an interrupt causes a CPU execution pipeline stall. The contents of the pipeline are usually discarded and the state of CPU registers at the completion of the last executed instruction are preserved by storing them in main memory. Subsequently, the CPU will be directed (or “jump”) to a known address determined by the interrupt controller configuration; in some cases this address is provided with the interrupt. Hence, execution at this new address creates a new state by loading all the registers with context related to the interrupt. This load requires reading the new information (usually out of main memory which may have been cached). Often times the new code sequence (the interrupt service routine) will include reading status registers to determine the cause of the interrupt and/or related information that controls the code execution. When an interrupt routine is ended, the unload/reload sequence is repeated this time restoring the state prior to the interrupt by reading the data back off of the “STACK”. However, there is a long delay in these unload and reload sequences which usually happens at a frequency slower than that of the actual CPU due to the inherently slower nature of system memory or IO space reads.
For the example of performing a context switch for interrupt processing, the interrupt cycle requires both a context switch and potentially a read of an external device to gain contextual information for proper interrupt handling. A context switch allows for clearing the instruction pipeline, changing the memory configuration to correspond to the new context, and restarting pipeline execution in the next context. Therefore, the impact of interrupt processing can and does continue to increase with processor frequency. Present solutions are inefficient for handling context switches.